1940 – PN junction

Russel Ohl at Bell Labs develops the PN junction that produces 0.5 volts when exposed to light.

 

1945 – Transistor invented [1],[2],[3],[4]

In 1945, Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William Shockley, included, John Bardeen, Walter Brattain and others. In 1947 Bardeen and Brattain succeeded in creating an amplifying circuit utilizing a point-contact “transfer resistance” device that later became known as a transistor. Bardeen and Brattain’s device was the Point Contact Transistor the first transistor. In 1948, Bardeen and Brattain filed for a patent, that in 1950 was issued to Bell Labs – U.S. patent # 2,524,035, “Three Electrode Circuit Element Utilizing Semiconductive Materials”.

 

1951 – Junction Transistor invented [1],[2],[3],[4]

In 1951, William Shockley developed the junction transistor, a more practical form of the transistor, the point contact transistor was difficult to produce and was replaced by the junction transistor by the mid fifties. By 1954 the transistor was an essential component of the telephone system. Bell labs also licensed the transistor to other companies (for a royalty) and the transistor first appeared in hearing aids followed by radios. In 1956 the importance of the invention of the transistor by Bardeen, Brattain and Shockley was recognized by the Nobel Prize in physics.

 

1952 – Single crystal silicon is fabricated [5]

 

1952 – Integrated Circuit concept published

English radar scientist Geoffrey W.A. Dummer publishes the concept of the integrated circuit in Washington D.C. on May 7, 1952. “Solid block [with] layers of insulating materials”. In 1956 Dummer unsuccessfully attemped to build an integrated circuit.

 

1954 – First commercial silicon transistor [1]

On May 10, 1954, Texas Instruments announced the commercial availability of grown-junction silicon transistors. These first silicon transistors were constructed by cutting a rectangular bar from a silicon crystal that was grown from a melt containing impurities. Silicon transistors were less expensive to produce and operated at higher temperature than germanium transistors.

 

1954 – Oxide masking process developed [5]

Bell Labs developed the oxidation, photomasking, etching, diffusion process that underlies IC production to this day.

 

1954 – First Transistor Radios [23]

Industrial Development Engineer Associates produced the Regency TR-1, the worlds first commercially marketed transistor radio. The radio had a four transistor circuit employing Texas Instruments Germanium transistors.

 

1955 – First field effect transistor

Bell Labs fabricated the first field effect transistor.

 

1958 – Integrated circuit invented [1],[6]

In July of 1958, Jack Kilby was a recent hire at Texas Instruments. Not having accrued enough vacation time yet, Kilby was at work at TI during a summer vacation period that most everyone else had off. On July 24, 1958 in the quiet of the miniaturization lab, Kilby wrote in his lab notebook that circuit elements such as resistors, capacitors, distributed capacitors and transistors, if all made of the same material, could be included in a single chip. By September 12th 1958 Kilby had built a simple oscillator IC with five integrated components. In 1959 Kilby applied for a patent and Texas Instruments was issued U.S. patent # 3,138,743 for “Miniaturized electronic circuits”. In 2000 the importance of the IC was recognized when Kilby shared the Nobel prize in physics with two others. Kilby was sited by the Nobel committee “for his part in the invention of the integrated circuit”.

 

1959 – Planar technology invented [1]

Kilby’s invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity. By late 1958 Swiss-born physicist – Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions. Czech-born physicist – Kurt Lehovec of Sprague Electric developed the technque of using PN junctions to electrically isolate components. In 1959, Robert Noyce also of Fairchild had the idea to create an integrated circuit by combing Hoerni’s and Lehovec’s processes and evaporating a thin metal layer over the circuits. The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuits and is the process used today.

 

1960 – Epitaxial deposition developed [7]

Bell Labs developed the technique of Epitaxial Deposition whereby a single crystal layer of material is deposited on a crystalline substrate. Epitaxial deposition is widely used in bipolar and sub-micron CMOS fabrication.

 

1960 – First MOSFET fabricated [5],[7]

Kahng at Bell Labs fabricates the first MOSFET.

 

1960 – 0.525 inch silicon wafers introduced [24]

 

1961 – First commercial ICs [13]

Fairchild and Texas Instruments both introduce commercial ICs. 1962 – Transistor-Transistor Logic invented [5]

 

1962 – Semiconductor industry surpasses $1-billion in sales [14] 1963 – First MOS IC [13]

RCA produces the first PMOS IC.

 

1963 – CMOS invented [15]

Frank Wanlass at Fairchild Semiconductor originated and published the idea of complementary-MOS (CMOS). It occurred to Wanlass that a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to prove the concept with discrete devices. Enhancement mode NMOS transistors were not yet available and so Wanlass was used a depletion mode device biased to the off-state. Amazingly CMOS shrank standby power by six orders of magnitude over equivalent bipolar or PMOS logic gates. On June 18, 1963 Wanlass applied for a patent. On December 5th 1967 Wanlass was issued U.S. Patent # 3,356,858 for “Low Stand-By Power Complementary Field Effect Circuitry”. CMOS forms the basis of the vast majority of all high density ICs manufactured today.

 

1964 – First commercial contact printer

Contact printing was the work-horse technology for exposing patterns onto IC wafers into the 1970s.

1964 – 1 inch silicon wafers introduced [24]

 

1965 – Moore’s law [16]

In 1965 Gordon Moore, director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled “Cramming more components onto integrated circuits”. In the paper Moore observed that “The complexity for minimum component cost has increased at a rate of roughly a factor of two per year”. This observation became known as Moore’s law, the number of components per IC double every year. Moore’s law was later amended to, the number of components per IC doubles every 18 months. Moore’s law hold to this day.

 

1965 – 100-bit shift register [8]

100-bit shift register with 600 transistors – GME, 21-bit static shift register with 160 transistors – GI, binary-to-digital decoder with 150 transistors – TI.

1966 – Self Aligned Gate MOSFET

Bower and Dill disclose the self aligned gate MOSFET (SAGFET) in a paper entitled

“Insulated Gate Field Effect Transistors Fabricated Using the Gate as Source-Drain Mask” [25], presented at the 1966 IEDM. The self aligned transitor was first concieved by Bower in 1965 [26]. The slef aligned transistor is the building block of all modern MOSFET technologies.

 

1966 – 16-bit bipolar memory [1]

IBM introduced a 16-bit bipolar memory chip in a System/360 Model 95 they developed for NASA. 1966 – First bipolar logic [5]

Motorola Emitter-Coupled-Logic (ECL) 3 input gate. 1966 – Single transistor DRAM cell invented [1]

Dr. Robert Dennard at IBM attended a talk on work in thin film magnetic memory. The magnetic memory team used “a piece of magnetic material and a couple of lines passing near it’ to store a bit of information. Several months later Dennard developed the idea that a bit could be stored by charging or discharging a capacitor and a single FET could be used to control the process. The single transistor DRAM cell. Virtually all modern DRAMs are based on the 1 transistor cell.

 

1966 – 1.5 inch silicon wafers introduced [24]

 

1967 – Floating gate disclosed

Kahng and Sze of Bell labs disclosed the use of floating gate devices for memory applications in the Bell System Technical Journal. Floating gates a very common technique used to make EEPROMs.

 

1967 – MNOS disclosed

Wegener, Lincoln, Pao, O’Connell and Oleksiak disclosed the NMOS transistor and it’s use in memory. Floating gates are a technique used to make EEPROMs. 1968 – 64-bit bipolar array chip [1]

IBM introduced a 64-bit bipolar array chip as a high speed memory buffer in the System/360 Model 85. The chip contained 64 storage cells and 664 components. 1969 – BiCMOS invented [I]

Lin, Ho, Iyer and Kwong disclose a “Complementary MOS-Bipolar Transistor Structure” at IEDM.

 

1970 – 1st NMOS IC [13]

Cogar, et.al., at IBM fabricate metal gate NMOS

1970 – First commercial DRAM – 1Kbits [9],[12]

In approximately 1969, William Regitz of Honeywell was looking for a semiconductor company to share in the development of a novel DRAM cell developed by himself or one of his coworkers. Intel was very interested in the technology and started a development program that initially produced the i1102, and although working parts were produced there were problems with the 1102. Based on work Ted Hoff had done looking at possible 3 transistor DRAM cell topologies, and the idea of a buried contact, probably by Ted Rowe, a schematic for an alternative part was developed by Leslie Vadasz and Joel Karp and the chip design was assigned to Bob Abbott. The resulting product was the i1103 and was introduced to the market in October 1970. The part originally had yield issues and John Reed, the product engineer had to make several revisions to the part before “good” yields and performance were achieved. The i1103 was manufactured on a 6 mask silicon gate PMOS process with 8µm minimum features. The resulting product had a 2,400µm2 memory cell size, a die size just under 10mm2 and sold for around $21.

 

1970 – IBM replaces magnetic memory with transistor based memory [1]

The IBM System/370 Model 145 introduced all transistor memory.

 

1970 – 2.25 inch silicon wafers introduced [24]

 

1971 – UVEPROM invented [11]

Shortly after joining Intel in 1969 and after the 1kbit DRAM was released, Dov Frohman invented UVEPROM an electrically programmable memory that holds the programmed values until erased by intense ultraviolet light. Frohman invented, developed, designed and fabricated the first UVEPROM. 1971 – Microprocessor invented [10],[8],[11]

By 1969 the concept of a programmable processor (microprocessor) had been around the industry for some time, but no one had the ability to fabricate anything sufficiently complex. Intel had recently developed a silicon gate process that offered the ability to fabricate more complex circuits than other manufacturers had at the time. Japanese calculator company Busicom asked Intel to produce a 12 chip set for desktop calculators, and although Intel was focused on memory at the time they were struggling enough to consider the project. Ted Hoff at Intel felt that the design 12 chip design was too complex and decided to look at a programmable solution. The combination of the Busicom application and the new Intel process capability came together and Intel management decided to support the project accepting a contract for $60,000. Hoff designed a simple instruction set that could be implemented in relatively few transistors. For 6 months the project languished until 1970 when Federico Faggin joined Intel and was assigned the task of designing the chip. On his first day of work Faggin was confronted by Masatoshi Shima, a Busicom representative disappointed with the lack of progress of the project over the last six months. After some negotiations Busicom agreed to continue the project and after 8 months of 12 to 16 hour days the first silicon came out – non-functional. The problem was simple manufacturing error and by 1971 the 4004 the first 4-bit microprocessor was in production. The 4004 was a 3 chip set with a 2kbit ROM chip, a 320bit RAM chip and the 4bit processor each housed in a 16 pin DIP package. The 4004 processor required roughly 2,300 transistors to implement, used a silicon gate PMOS process with 10µm linewidths, had a 108KHz clock speed and a die size of 13.5mm2. Ironically Intel didn’t own the design and it wasn’t until Busicom asked for a price reduction that Intel received rights to the technology. By 1972 Faggin working with Shima, who had now joined Intel, developed the 8008 an 8-bit successor to the 4004. In 1974 Intel introduced the 8080, the first commercially successful microprocessor.

 

1972 – Digital Signal Processor invented

John Murtha, et.al., of Westinghouse filed for a patent on a “Programmable Digital Signal Processor”. The patent not only discloses the DSP but also describes saturation arithmetic, a key concept to prevent overflow that is ubiquitous in DSPs today. In 1974 U.S. Patent # 3,812,470 was issued to Murtha, et.al., and assigned to Westinghouse.

 

1972 – MOSFET Scaling [18]

In 1970, IBM was searching for a technology to lower the cost of RAM to make it competitive on a cost/bit basis with magnetic disks. Dale Critchlow’s group at IBM was charged with achieving 1 millicent/bit. Reporting to Critchlow was a group managed by Bob Dennard and including Fritz Gaensslen and Larry Kuhn. Bob Dennard, the inventor of the 1 transistor DRAM cell was a strong proponent of that approach, but realized that a significant shrink of the cell size was required to meet the cost target. Critchlow and Dennard decided to take an existing 5µm technology shrink it to 1µm. Dennard and Gaensslen derived a constant electric field scaling theory and it’s limitations. The remarkable result was that if the electric field was kept constant when a MOSFET was shrunk, nearly every other transistor characteristic improved! The group went on to produce devices with 1µm design rules and a paper was presented on the results at IEDM in 1972. The work continued to be refined and at 1974 IEDM Dennard, et.al., presented the classic paper on scaling “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions”. Although it was not generally recognized at the time, scaling theory would eventually end the supremacy of bipolar ICs. Bipolar technology does not scale the way MOSFET technology does and by the early nineties MOSFET technology was the dominant high-end – high-speed technology.

 

1972 – Intel 8008

The 8008 was the 8 bit successor to the 4004 and was used in the Mark-8 computer, one of the first home computers [22]. Manufactured in the same silicon gate PMOS process with 10µm linewidths, 1 polysilicon layer and 1 metal layer, the 8008 had 3,500 transistors, a 200kHz clock speed and a 15.2mm2 die size.

 

1973 – Commercial BiCMOS ICs [17]

Polinsky, Schade and Keller of RCA disclose “CMOS-Bipolar Monolithic Integrated Circuit Technology” at IEDM. The metal gate BiCMOS technology is used to make operational amplifiers.

 

1973 – Projection Printer Invented [13]

Perkin Elmer (now SVG Lithography) introduces the projection printer. The combination of projection printing with positive photoresist revolutionized photolithography in the mid 1970s. Defect rate were dramatically lower without mask-wafer contact and yields improved substantially.

 

1973 – 3 inch silicon wafers introduced [24]

 

1974 – First 4Kbit DRAM with 1T Cell [12]

The 4Kbit DRAM introduced the 1 transistor cell and the silicon gate NMOS process. The 3T to 1T memory cell transition is the first major DRAM transition. The silicon gate NMOS process required 6 masks and had 8µm minimum features. The resulting product had a 1,280µm2 memory cell size, a die size of approximately 15mm2 and sold for around $18 at introduction.

 

1974 – Intel 8080

The 8080 was used in the Altair computer [22]. The 8080 was manufactured in a silicon gate NMOS process with 6µm linewidths, 1 polysilicon layer and 1 metal layer, the 8080 had 6,000 transistors, a 2MHz clock speed and a 20.0mm2 die size.

 

1975 – 100mm silicon wafers introduced [24]

 

1976 – 16Kbit DRAM introduced [12]

The 16Kbit DRAM introduced dual polysilicon layers allowing more efficient memory cell layout. The single to dual polysilicon layer transition is the second major DRAM transition. The dual polysilicon NMOS process required 7 masks and had 5µm minimum features. The resulting product had a 500µm2 memory cell size, a die size of approximately 19mm2 and sold for around $33 at introduction.

 

1978 – Intel 8086/8088

The 8088 was selected by IBM for the IBM PC, the biggest semiconductor design win ever. The 8088/8086 were manufactured in a silicon gate NMOS process with 3µm linewidths, 1 polysilicon layer and 1 metal layer, the 8088/8086 had 29,000 transistors, a 5 to 10MHz clock speed and a 28.6mm2 die size. Both processors were identical 16 bit designs with the 8086 having a 16 bit bus and the 8088 having an 8 bit bus.

 

1978 – Step and Repeat System invented

GCA introduces the step and repeat system for wafer exposure. Step and repeat revolutionizes photolithography in the eighties increasing resolution and enabling linewidth shrinks [13].

 

1978 – Semiconductor Industry passes $10-billion. [14]

 

1979 – 64Kbit DRAM introduced [12]

The 64Kbit DRAM was produced on a dual polysilicon NMOS process requiring 8 to 10 masks and had 3µm minimum features. The resulting product had a 180µm2 memory cell size, a die size of approximately 31mm2 and sold for around $47 at introduction.

 

1979 – 125mm silicon wafers introdcued [24]

 

1980 – Modern DSP commercially available [19]

Based on our definition of a “modern” DSP as a single chip, programmable stand-alone solution with parallelism in multiply-add and memory access, the first commercially available DSPs were introduced in 1980 by Lucent and NEC. Earlier parts such as the AMI S2811 in 1978 required a microprocessor for initialization and configuration, and the Intel 2920 in 1979 lacked a multiplier.

 

1980 – IBM selects Intel 8088 for the PC.

 

1981 – 150mm silicon wafers introduced [24]

 

1982 – 256Kbit DRAM

Initially, the 256Kbit DRAM was produced on a dual polysilicon NMOS process requiring 8 to 10 masks and had 2µm minimum features. The resulting product had a 70µm2 memory cell size, a die size of approximately 45mm2 and sold for around $51 at introduction. Later versions converted to CMOS with 1.5µm features. 1982 – Intel 80286

The 80286 was a major step forward in processor performance while maintaining backward compatibility for software. The 80286 was manufactured in a silicon gate CMOS process with 1.5µm linewidths, 1 polysilicon layer and 2 metal layers, the 80286 had 134,000 transistors, a 6 to 12MHz clock speed and a 68.7mm2 die size. 1983 – 1st CMOS DRAM [13]

Intel develops a 1Mbit CMOS DRAM, the 1st CMOS DRAM. Ironically Intel soon exits the DRAM business. 1983 – EEPROM Invented [20]

16Kbit EEPROMs introduced based on the floating gate and MNOS. 1984 – Flash memory invented

Masuoka, et.al., of Toshiba disclosed at IEDM the idea of an electrically programmable – non-volatile memory that could be rapidly erased in blocks (Flash is for flash erase). The architecture also required only a single transistor per memory cell rather than 2 transistors per cell the way standard EEPROM did. 1985 – Commercial Flash memory introduced

Toshiba introduces a 256Kbit flash memory chip. 1985 – Intel 80386DX

The 80386 was the first 32 bit processor from Intel. The 80386 was manufactured in a silicon gate CMOS process with 1.5µm linewidths, required 10 mask layers and had 1 polysilicon layer and 2 metal layers, the 80386 had 275,000 transistors, a 16 to 33MHz clock speed and a 104mm2 die size.

 

1985 – 200mm silicon wafers introduced [24]

 

1986 – ETOX style Flash introduced [21]

256Kbit introduced by Intel. ETOX is the most common style of Flash today. 1986 – 1Mbit DRAM

The 1Mbit DRAM introduced the use of non-planar DRAM memory cells such as stacked or trench cells, although some planar cells were also produced. The transition from a planar to a non planar cell is the third major DRAM transition. The 1Mbit DRAM was produced on a CMOS process requiring approximately 18 masks with 2 to 3 polysilicon layers and 1.2µm minimum features. The resulting product had a 25µm2 memory cell size, a die size of approximately 70mm2 and sold for around $100 at introduction. 1988 – 4Mbit DRAM

The 4Mbit DRAM was produced on a CMOS process requiring 20 to 25 masks, with 2 to 3 polysilicon layers, 2 metal layers and 0.8µm minimum features. All 4Mbit memory was produced with a stacked or trenched cell, 1Mbit DRAM was the end of the planar cell. The resulting product had a 12µm2 memory cell size, a die size of approximately 95mm2 and sold for around $124 at introduction. Later versions utilized smaller linewidths to shrink the die. 1989 – Intel 80486DXTM

The 80486 was the first processor from Intel to include a floating point coprocessor on chip and execute 1 instruction per clock cycle. The 80486 was manufactured in a silicon gate CMOS process with 1.0µm linewidths, required 12 mask layers and had 1 polysilicon layer and 3 metal layers, the 80486 had 1.2 million transistors, a 25 to 50MHz clock speed and a 163mm2 die size.

 

1991 – 16Mbit DRAM

The 16Mbit DRAM was produced on a CMOS process with 3 to 4 polysilicon layers, 2 metal layers and 0.5µm minimum features. The resulting product had a 4.2µm2 memory cell size, a die size of approximately 130mm2 and sold for around $275 at introduction. Later versions utilized smaller linewidths to shrink the die.

1993 – Intel PentiumTM

The Pentium is the first processor from Intel capable of executing more than 1 instruction per clock cycle. The Pentium was manufactured in a silicon gate BiCMOS process with 0.8µm linewidths, required 18 mask layers and had 1 polysilicon layer and 3 metal layers, the Pentium had 3.1 million transistors, a 60 to 66MHz clock speed and a 264mm2 die size. 1994 – Semiconductor Industry passes $100-billion. 1994 – 64Mbit DRAM

The 64Mbit DRAM was produced on a CMOS process with 3 to 5 polysilicon layers, 2 to 3 metal layers and 0.35µm minimum features. The resulting product had a 1.5µm2 memory cell size, a die size of approximately 170mm2 and sold for around $575 at introduction. Later versions utilized smaller linewidths to shrink the die. 1995 – Intel Pentium ProTM

The Pentium Pro introduced a dual cavity package with the Pentium Pro chip and a Cache chip housed together. The bus to the cache ran at the same speed as the processor. The Pentium Pro was manufactured in a silicon gate BiCMOS process with 0.35µm linewidths, required 20 mask layers and had 1 polysilicon layer and 4 metal layers, the Pentium Pro had 5.5 million transistors, a 150 to 200MHz clock speed and a 310mm2 die size.

 

1996 – 300mm silicon wafers introduced [24]

 

1997 – Intel Pentium IITM

The Pentium II introduced single in-line cartridge housing the processor chip and standard cache chips running at ½ the processor speed. The Pentium II was manufactured in a silicon gate CMOS process with 0.35µm linewidths, required 16 mask layers and had 1 polysilicon layer and 4 metal layers, the Pentium II had 7.5 million transistors, a 233 to 300MHz clock speed and a 209mm2 die size. 1998 – 256Mbit DRAM

The 256Mbit DRAM was produced on a CMOS process with 4 to 5 polysilicon layers, 2 to 3 metal layers and 0.25µm minimum features. The 256Mbit DRAM introduced the use of high-k dielectrics, although many parts are also produced without high-k, high-k dielectric represents the fourth major DRAM transition. The resulting product had a die size of approximately 204mm2 and sold for around $575 at introduction. Later versions utilized smaller linewidths to shrink the die. 1999 – Intel Pentium IIITM

The Pentium III returned to a more standard PGA package and integrated the cache on chip. The Pentium III was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium III had 28 million transistors, a 500 to 733MHz clock speed and a 140mm2 die size.

 

2000 – Intel Pentium 4TM  (180nm)

The Pentium 4 introduced an integer unit running at twice the processor speed. The Pentium 4 was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium 4 had 42 million transistors, a 1,400 to 1,500MHz clock speed and a 224mm2 die size.

2001 – Intel Pentium 4TM  (130nm) The 130nm Pentium 4 incorporates 55 million transitors and yet still provides a die size shrink to 146.0 mm2. At 130nm the process is a single polysilicon CMOS process with 6 copper layers and requires an estimated 26 mask. 2002 – 1Gb DRAM enters volume production

Utilizing a 26 mask, 6 polysilicon layer (stacked DRAMs) 130nm process volume, 1Gb DRAMs had a 203.6 mm2 die size and an average selling price for 2002 of $50.

2003 – Intel Pentium 4TM  (90nm) Intel introduced a 90nm process in 2003. The single polysilicon CMOS process has 7 layers of coper metal and requires an estimated 29 mask layers. The 90nm Pentium 4 has 125 million transitors and the die size shrinks to 112 mm2. The most notable part of the 90nm process is the introduction of strained silicon by using embedded silicon germanium and tensile stress layers.

2005 – Intel Pentium 4TM  (65nm) Intel introduced a 65nm process in 2005. The single polysilicon CMOS process has 8 layers of coper metal and requires an estimated 31 mask layers. The 65nm Pentium 4 has 169 million transitors and the die sizeis 189.9 mm2. Intel soon swithced to the new smaller “Core” design.

2007 – Intel Core 2 Duo (45nm)

Intel’s 45nm debuted in 2007 as the first high-k gate oxide with dual metal gates in production. The 45nm process is a single polysiliocn process with 9 copper layers and requires and estimated 36 mask layers. The 45nm Core 2 Duo die size is 105.78mm2 and packs in 410 million transitors.

 

 

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